As a dimension of a semiconductor device becomes smaller continuously, a key size of the semiconductor device, i.e. a gate length, becomes shorter continuously. When the gate length of a metal oxide semiconductor field effect transistor (MOSFET) decreases to below 45 nm, the MOSFET exhibits more significant short channel effects (SCE). The short channel effects include threshold voltage drift, lower carrier mobility, Drain Induced Barrier Lowering (DIBL), and other effects of the semiconductor device.
One known approach for suppressing the short channel effects introduces an additional semiconductor layer between a semiconductor substrate and an SOI structure. The additional semiconductor layer is ion doped to form a backgate structure, to which a bias voltage is applied so as to adjust the threshold voltage of the semiconductor device. However, in such an approach, different bias voltages are applied to backgates of pMOSFETs and nMOSFETs so as to adjust the threshold voltages in different manners, which means that different backgate contacts should be provided for the pMOSFETs and the nMOSFETs. Consequently, the backgate contacts occupy an increased footprint, which hinders further improvement of the integration level of a semiconductor device.
In view of this, it is still desirable for novel semiconductor structures and methods for manufacturing the same, such that the threshold voltages of the pMOSFET and the nMOSFET can be adjusted respectively and the integration level can be improved.